The communication and storage system block diagrams are depicted in FIG. 1. Low Density Parity Check (LDPC) codes have been recognized as the class of codes that can achieve performance very close to theoretical maximum. Based on these attributes LDPC codes have been adopted for use in various communication standards, Wi-Fi 802.11, DVB, etc. The LDPC codes are known to exhibit the error floor at high Signal-To-Noise Ratios (SNR) attributed to structures known as trapping sets, absorbing sets or near code words. The error floor is degradation in performance of the LDPC codes that causes diminishing improvements in performance with increase in SNR.
The error floor behavior of LDPC codes can be mitigated to some extent by careful code construction, by using a particular internal structure and by increasing the length of the code. Each approach has its drawbacks. The code construction with error floor optimization becomes very difficult for code lengths above 3000-4000 bits due to an exponential increase in the number of structures that have to be considered by optimization algorithm. Construction of LDPC codes with particular internal structure, specifically very high column weight, is known to lower the error floor, but this method has a substantial impact on the hardware implementation of the LDPC decoder, particularly the throughput of the decoder and power consumption. Furthermore, actual performance cannot be guaranteed and has to be measured through simulations, which is often unfeasible.
Increasing the length of the code has limited impact on error floor performance, but it could be viable option for particular code rates and relaxed error floor requirements. This option also impacts the hardware implementation by requiring large memories to store the long code.
The stringent error recovery requirements, especially in storage systems like Hard Disk Drives (HDD) and Solid State Drives (SSD), are impossible to verify in practice by either software or hardware simulation, so neither of the above mentioned methods provides guaranteed performance. Therefore the error floor presents a significant challenge when designing the system with LDPC codes. This is also of great importance in the production of Hard Disk Drives (HDD), where performance of the product must be estimated during production in a very short time. The proposed invention, described below, enables such estimation so that performance is guaranteed. Therefore, the proposed method can provide significant saving in production time of the HDD's.